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Target Configuration Space
Table 7-18 · Backend Address Register 54 Hex (ENABLE_DIRECTDMA = 0)
Bit(s)
1:0
31:2
Bit(s)
31:0
Type
RO
RW/
RO
Type
RW
Description
Set to '00'. PCI transfers must be on DWORD boundaries.
This location contains the backend start address and will increment during the DMA transfer. The width of this
register depends on the MADDR_WIDTH parameter. If MADDR_WIDTH is set to 20, bits 31:20 of this register
are read-only and set to 0.
If using 64-bit transfers, bit 2 should be set to 0.
Table 7-19 · Backend Address and Data Register 54 Hex (ENABLE_DIRECTDMA = 1)
Description
When DMA_BAR = '111' ( Table 7-21 on page 113 ), this register contains the 32-bit data value that will be written
to or read from the PCI bus.
When DMA_BAR ≠ '111', this specifies the backend address.
The core will ignore bits 1 and 0 to align the transfer count to a DWORD boundary. If using 64-bit transfers, bit 2
should also be set to 0.
Table 7-20 · DMA Transfer Count 58 Hex
Bit(s) Type
Description
Specifies the size of a DMA transfer in bytes. For 32-bit operation, this should be a multiple of four, and for 64-bit
31:0
RW
operations, a multiple of eight. Bits 1:0 are read-only and return 0. The maximum transfer size is set by the
DMA_COUNT_WIDTH parameter. When set to zero, 2 DMA_COUNT_WIDTH bytes will be transferred.
Table 7-21 · DMA Control Register 5C Hex
Bit(s) Type
DMA Status
00: No Error
Description
1:0
2
3
RW
RW
RW
01: Master Abort
10: Parity Error
11: Target Abort
DMA Done
A '1' indicates that the DMA transfer is complete. Writing a '0' clears this bit.
DMA Request
Writing a '1' will initiate a DMA transfer, and the bit will remain set until the DMA transfer completes or an error
occurs (Master abort or Target abort). This bit can only be set if the bus Master enable bit is set in the PCI Command
register ( Table 7-6 on page 108 ).
v4.0
113
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